Digital Electronics and Computer Organisation. 2019

 

Section-A 

1. Give the truth table and symbol for X-OR gate.

Symbol for XOR Gate:

The symbol for an XOR gate is:

      A ----|      |
            |  ⊕   |---- Output
      B ----|      |

Truth Table for XOR Gate:

Input A	Input B	Output (A ⊕ B)
0	0	0
0	1	1
1	0	1
1	1	0

Explanation:

• The XOR (Exclusive OR) gate gives an output of 1 when the inputs are different and 0 when the inputs are the same.

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2. What is Subtractor?

Explanation:

A Subtractor is a combinational circuit that performs the subtraction of two binary numbers. Subtractors can be of two types:

1. Half Subtractor: Subtracts two bits and provides the difference and borrow.
2. Full Subtractor: Subtracts three bits (including a borrow from the previous stage).

Half Subtractor Truth Table:

Input A	Input B	Difference (D)	Borrow (B)
0	0	0	0
0	1	1	1
1	0	1	0
1	1	0	0

Expression:

• Difference (D) = $A \oplus B$
• Borrow (B) = $\overline{A}B$

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3. Define Associative Memory.

Explanation:

• Associative memory (also called Content-Addressable Memory, CAM) is a type of memory that enables data to be retrieved based on its content rather than its specific address.
• It works like a database query, where data is fetched if it matches a specific criterion.

Key Features:

1. Faster data retrieval compared to traditional memory.
2. Often used in cache memory and network routing tables.

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4. Give the applications of shift registers.

Explanation:

Shift Registers are sequential circuits that shift their data in a specific direction (left or right) when triggered by a clock signal. They have the following applications:

1. Data Storage: Temporarily stores data in digital systems.
2. Data Transfer: Transfers data serially (one bit at a time) or in parallel.
3. Counters: Used in ring counters and Johnson counters.
4. Digital Signal Processing: Shifts data for operations like delays and filtering.
5. Serial-to-Parallel Conversion: Converts serial input data into parallel output.
6. Parallel-to-Serial Conversion: Converts parallel input data into serial output.

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5. State the Boolean Distributive Law.

Explanation:

The Boolean Distributive Law states that:

1. $A \cdot (B + C) = (A \cdot B) + (A \cdot C)$
2. $A + (B \cdot C) = (A + B) \cdot (A + C)$

Verification:

For $A \cdot (B + C) = (A \cdot B) + (A \cdot C)$:

• Let $A = 1, B = 0, C = 1$:
  • LHS: $1 \cdot (0 + 1) = 1 \cdot 1 = 1$
  • RHS: $(1 \cdot 0) + (1 \cdot 1) = 0 + 1 = 1$

Thus, the distributive law is valid.

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Section-B 

6. Simplify the given function using K-maps

F(A, B, C, D) = Σ(0, 2, 3, 5, 7, 9, 11, 13, 14)

Step-by-Step Solution:

1. Construct a 4-variable K-map:

   • Label the rows and columns based on the combinations of A, B, C, and D.

2. Fill the K-map with 1s for the given minterms:

   • Place 1 in cells corresponding to the minterm indices: $0, 2, 3, 5, 7, 9, 11, 13, 14$.
   • All other cells will contain 0.

K-Map:

         CD
     00  01  11  10
AB
00   1   0   1   1
01   0   1   1   1
11   1   1   0   1
10   0   1   1   0

3. Group the adjacent 1s:

   • Group 8 adjacent 1s, 4 adjacent 1s, or 2 adjacent 1s, ensuring minimal groups for simplicity.
   • Groups for this problem:
     • Group 1: $A'B'D$ (covers minterms 0, 2, 8, 10)
     • Group 2: $B'C'D$ (covers minterms 2, 3, 10, 11)
     • Group 3: $ACD'$ (covers minterms 5, 7, 13, 14)

4. Write the simplified expression:

   • $F(A, B, C, D) = A'B'D + B'C'D + ACD'$

Final Answer:

$F(A, B, C, D) = A'B'D + B'C'D + ACD'$

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7. Derive the Boolean expression for the logic circuit shown below:

Step-by-Step Solution:

1. Analyze the Circuit:

   • The given circuit is a combination of AND, OR, and NOT gates.
   • Trace the inputs $A, B, C, D$ and observe how they are connected through the gates.

2. Derive Expressions at Each Gate:

   • First AND gate: $X_1 = A \cdot B$
   • Second AND gate: $X_2 = C \cdot D$
   • OR gate: $F = X_1 + X_2$

3. Substitute Back:

   • $F = (A \cdot B) + (C \cdot D)$

Final Answer:

$F = (A \cdot B) + (C \cdot D)$

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8. Draw RS flip-flop and explain its working:

Diagram of RS Flip-Flop:

An RS flip-flop can be implemented using two cross-coupled NOR gates or NAND gates.

NOR Gate Implementation:

        S -----|     |------- Q
               | NOR |
        Q'-----|     |
               |     |
        R -----| NOR |------- Q'

Working:

• The RS flip-flop is a bistable multivibrator with two stable states, used for storing one bit of data.
• Inputs: $S$ (Set) and $R$ (Reset).
• Outputs: $Q$ (normal) and $Q'$ (complement).

Truth Table:

S (Set)	R (Reset)	Q (Output)	Q' (Complement)	Description
0	0	No Change	No Change	Holds previous state
0	1	0	1	Reset state (Q = 0)
1	0	1	0	Set state (Q = 1)
1	1	Invalid	Invalid	Not allowed (indeterminate)

Explanation:

1. Set Condition: When $S = 1$ and $R = 0$, $Q$ becomes 1 (Set state).
2. Reset Condition: When $S = 0$ and $R = 1$, $Q$ becomes 0 (Reset state).
3. Hold Condition: When $S = 0$ and $R = 0$, the flip-flop retains its previous state.
4. Invalid State: When $S = 1$ and $R = 1$, both $Q$ and $Q'$ become 0, which is not allowed in proper operation.

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Section-C 

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9. Give the difference between the following:

(i) SRAM vs DRAM

Feature	SRAM (Static RAM)	DRAM (Dynamic RAM)
Storage Element	Uses flip-flops (6 transistors per cell)	Uses capacitors and transistors (1 transistor per cell)
Speed	Faster due to no need for refresh cycles	Slower due to the need for constant refresh
Power Consumption	High (as flip-flops are always powered)	Low (refreshing consumes less power overall)
Density	Lower (fewer cells fit on a chip)	Higher (more cells per unit area)
Cost	More expensive	Less expensive
Usage	Used in cache memory (high-speed memory)	Used in main memory

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(ii) Registers vs Counters

Feature	Registers	Counters
Definition	A set of flip-flops used to store binary data	A sequential circuit that counts pulses
Function	Used for temporary data storage	Used to count events or generate sequences
Types	Shift registers, parallel registers, etc.	Asynchronous and synchronous counters
Operation	Holds or shifts data	Increments or decrements its value
Usage	Found in processors for data manipulation	Found in timers, clocks, and frequency dividers

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10. Design 5-Mod counters using J-K flip-flops

Step-by-Step Solution:

1. Understand the Requirement:

   • A 5-mod counter counts from 0 to 4 and then resets to 0.

2. Number of Flip-Flops:

   • To count up to 5 states, we need $n$ flip-flops such that $2^n \geq 5$. Hence, 3 flip-flops are required ($2^3 = 8$).

3. Truth Table:

   • The counter states will be $000, 001, 010, 011, 100$. After 100, it resets to 000.

4. Logic Design:

   • Use J-K flip-flops where $J$ and $K$ inputs control the toggling.
   • The output $Q$ of the flip-flops is connected in such a way that the count sequence follows 0 to 4.
   • Reset the flip-flops when $Q_2Q_1Q_0 = 101$ (count 5).

5. Circuit Diagram:

   • Connect the J and K inputs of each flip-flop as required for counting.
   • Add a reset logic circuit to force all flip-flops to 0 when the count reaches 5.

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(ii) What is cache memory? Why is it called high-speed memory?

Explanation:

• Cache Memory is a small, high-speed memory located between the CPU and main memory. It stores frequently accessed data and instructions to speed up the execution process.
• Why High-Speed? Cache memory is implemented using SRAM, which is faster than DRAM (used in main memory). It minimizes the time the CPU waits for data by storing data closer to the processor.

Design an 8x1 Multiplexer:

Definition:

• A Multiplexer (MUX) is a combinational circuit that selects one input from multiple inputs and forwards it to the output based on the select lines.

Steps:

1. Inputs: $D_0, D_1, D_2, ..., D_7$
2. Select Lines: 3 lines $S_0, S_1, S_2$ to choose one of 8 inputs.
3. Output: $Y = D_{selected}$.

Boolean Expression:

• $Y = S_2'S_1'S_0'D_0 + S_2'S_1'S_0D_1 + S_2'S_1S_0'D_2 + \dots + S_2S_1S_0D_7$.

Circuit Diagram:

• Connect 8 data inputs to an 8x1 MUX, controlled by the 3 select lines. Use AND, OR, and NOT gates to implement the selection logic.

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11. Describe the following terms:

(i) ROM:

• Read-Only Memory (ROM) is non-volatile memory that stores permanent data and instructions (e.g., firmware). Data in ROM cannot be modified easily.
• Types: PROM, EPROM, EEPROM.

(ii) PROM:

• Programmable ROM is a type of ROM that can be programmed once after manufacturing using a special device.

(iii) EPROM:

• Erasable Programmable ROM can be erased using ultraviolet (UV) light and reprogrammed.

(iv) RAM:

• Random Access Memory is volatile memory used as a temporary workspace for a CPU. It allows both read and write operations.

(v) Virtual Memory:

• Virtual Memory is a memory management technique that uses a portion of the hard drive as if it were RAM. It extends the available memory space for applications.

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13. Discuss various types of Logic Gates. Also, discuss their applications.

Types of Logic Gates:

1. Basic Gates:

   • AND Gate: Output is 1 if all inputs are 1.
   • OR Gate: Output is 1 if at least one input is 1.
   • NOT Gate: Outputs the complement of the input.

2. Universal Gates:

   • NAND Gate: Combines NOT and AND functionality. Any logic circuit can be built using NAND gates.
   • NOR Gate: Combines NOT and OR functionality. It is also a universal gate.

3. Special Gates:

   • XOR Gate: Output is 1 if the inputs are different.
   • XNOR Gate: Output is 1 if the inputs are the same.

Applications:

• AND Gate: Used in decision-making circuits where all conditions must be true.
• OR Gate: Used in alarm systems where any condition triggers the output.
• NOT Gate: Used in inverters.
• NAND/NOR Gates: Used in building any digital circuit as universal gates.
• XOR Gate: Used in error detection circuits.
• XNOR Gate: Used in equality checking circuits.

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