Digital Electronics and Computer Organisation. 2024

Section A of the given exam paper:

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Q1. NAND gate is known as a universal gate. Realize the basic gates from this universal gate.

Explanation:

• A NAND gate can perform all the basic logic gate operations: AND, OR, and NOT, making it a universal gate.
• Realization of Basic Gates:

  1. NOT Gate using NAND:

     • Connect both inputs of the NAND gate together. This configuration negates the input.
     • Truth Table:

       Input (A)	Output (Y = NOT A)
       0	1
       1	0

  2. AND Gate using NAND:

     • First, use a NAND gate with inputs A and B to get $\overline{A \cdot B}$.
     • Then, connect the output to another NAND gate configured as a NOT gate.
     • Output: $Y = A \cdot B$.

  3. OR Gate using NAND:

     • Use NOT gates (via NAND) to negate the inputs $A$ and $B$, then pass them through a NAND gate.
     • Output: $Y = A + B$.

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Q2. Differentiate between synchronous and asynchronous counters.

Explanation:

1. Synchronous Counters:

   • All flip-flops are triggered by the same clock pulse.
   • No propagation delay as all bits are updated simultaneously.
   • More complex design but faster.

2. Asynchronous Counters:

   • Flip-flops are triggered by different clock pulses (output of one acts as the clock for the next).
   • Slower due to propagation delay between flip-flops.
   • Simpler design but less efficient for high-speed operations.

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Q3. Describe SR Latch. Draw its logic circuit and its truth table.

Explanation:

• The SR Latch is a basic flip-flop made of two cross-coupled NOR or NAND gates.
• It has two inputs: Set (S) and Reset (R), and two outputs: Q and $\overline{Q}$.

Logic Circuit:

1. Using NOR gates:
   • Connect the output of one NOR gate to the input of the other.
   • Inputs $S$ and $R$ control the latch.

Truth Table:

S	R	Q	$\overline{Q}$
0	0	No Change	No Change
0	1	0	1
1	0	1	0
1	1	Invalid	Invalid

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Q4. Differentiate between static memory, dynamic memory, and auxiliary memory.

Explanation:

1. Static Memory (SRAM):

   • Uses flip-flops to store data.
   • Retains data as long as power is supplied.
   • Faster but expensive and requires more space.

2. Dynamic Memory (DRAM):

   • Uses capacitors to store data.
   • Needs periodic refreshing to retain data.
   • Slower but cheaper and more compact than SRAM.

3. Auxiliary Memory:

   • Non-volatile storage used for long-term data storage (e.g., hard disks, SSDs).
   • High capacity but slower than main memory.

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Q5. In computer memory, write down the different units for memory. A memory can store 1024 words, each having 8 bits. Represent this memory in K (Kilo).

Explanation:

• Memory Calculation:

  1. 1 word = 8 bits → $1024 \, \text{words} \times 8 \, \text{bits} = 8192 \, \text{bits}$.
  2. Convert bits to bytes: $8192 \, \text{bits} / 8 = 1024 \, \text{bytes}$.
  3. Convert bytes to kilobytes: $1024 \, \text{bytes} = 1 \, \text{KB}$.

• Different Units of Memory:

  • Bit (b)
  • Byte (B) = 8 bits
  • Kilobyte (KB) = $1024 \, \text{bytes}$
  • Megabyte (MB) = $1024 \, \text{KB}$
  • Gigabyte (GB) = $1024 \, \text{MB}$

Thus, the given memory is 1 KB.

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Section B of the exam paper:

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Q6. Minimize the following Boolean function using K-map:

F(A, B, C, D) = Σ(0, 3, 6, 7, 9, 13, 14, 15)

Explanation:

1. Steps to Minimize Using K-map:

   • A 4-variable K-map is used as the function has variables $A, B, C, D$.
   • The minterms (Σ) are placed in the corresponding cells of the K-map.

2. K-map Setup:

   AB \ CD	00	01	11	10
   00	0	3	7	6
   01	9	13	15	14
   11
   10

   • Place 1s in cells corresponding to the minterms $\{0, 3, 6, 7, 9, 13, 14, 15\}$.

3. Grouping of 1s:

   • Identify and group 1s into pairs, quads, or octets based on adjacency.
   • Derive simplified expressions for each group.

4. Final Simplified Expression:

   • The minimized Boolean expression for $F(A, B, C, D)$ is derived.

(I can create a detailed K-map layout for this if needed.)

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Q7. An AND gate has four inputs A, B, C, D and an output Y.

(i) Write the Boolean expression and sequential diagram.
Boolean Expression:
$Y = A \cdot B \cdot C \cdot D$

Sequential Diagram:

• Connect four inputs $A, B, C, D$ to an AND gate.
• The output $Y$ is high ($Y = 1$) only if all inputs are high.

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(ii) When does the above gate give high output? Draw the truth table.
Explanation:

• An AND gate gives a high output only when all inputs are 1.

Truth Table:

A	B	C	D	Y = $A \cdot B \cdot C \cdot D$
0	0	0	0	0
0	0	0	1	0
0	0	1	0	0
0	0	1	1	0
...	...	...	...	...
1	1	1	1	1

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(iii) For $Y$, write the Boolean expression and sequential diagram.
This is already answered in part (i).

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Q8. Describe Demultiplexer and design a 1:4 Demultiplexer using gates.

Explanation:

• A Demultiplexer takes one input and routes it to one of multiple outputs based on select lines.
• A 1:4 Demultiplexer has:
  • 1 data input (D).
  • 2 select lines (S1, S0).
  • 4 outputs (Y0, Y1, Y2, Y3).

Truth Table:

S1	S0	Output Y0	Output Y1	Output Y2	Output Y3
0	0	1	0	0	0
0	1	0	1	0	0
1	0	0	0	1	0
1	1	0	0	0	1

Circuit Design:

• Use 4 AND gates and 2 NOT gates:
  1. The NOT gates invert select lines $S1$ and $S0$ as needed.
  2. Each AND gate is connected to $D$ and a unique combination of $S1$ and $S0$.

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Section C of the exam paper:

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Q9 (a). Draw the logic circuit for the Boolean equation $Y = [AB (C + BD) + \overline{A}B]C$.

Step-by-Step Simplification:

1. Given Expression:

   $$Y = [AB (C + BD) + \overline{A}B]C$$

2. Simplify Step-by-Step:

   • Expand $AB(C + BD)$: $$AB(C) + AB(BD) = ABC + ABBD = ABC + ABD$$
   • Now, include the second term: $$[ABC + ABD + \overline{A}B]C$$
   • Distribute $C$ across the terms: $$(ABC \cdot C) + (ABD \cdot C) + (\overline{A}B \cdot C)$$
   • Since $C \cdot C = C$: $$ABC + ABCD + \overline{A}BC$$

3. Logic Circuit:

   • Use AND gates to implement terms $ABC$, $ABDC$, and $\overline{A}BC$.
   • Use OR gates to sum these terms.
   • Include NOT gate for $\overline{A}$.

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Q9 (b). Simplify the expression and draw the logic circuit for the simplified expression.

Simplified Expression:

From the expanded terms:

$$Y = BC(A + \overline{A})$$

Since $A + \overline{A} = 1$:

$$Y = BC$$

Logic Circuit for Simplified Expression:

• Use an AND gate with inputs $B$ and $C$.

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Q10. Draw the circuit of a serial-in parallel-out shift register. Draw and explain its working.

Explanation:

1. Definition:

   • A Serial-In Parallel-Out (SIPO) Shift Register takes data serially (bit-by-bit) at its input and outputs data in parallel after shifting.

2. Working:

   • The register consists of D flip-flops connected in series.
   • A clock signal controls the shifting process:
     • Input bit enters the first flip-flop.
     • On every clock pulse, data shifts from one flip-flop to the next.
   • After $n$ clock pulses (where $n$ is the number of flip-flops), all bits are available at the output.

3. Circuit Diagram:

   • Include $n$ D flip-flops in series.
   • Input data $D$ is connected to the first flip-flop.
   • Clock signal connects to all flip-flops.

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Q11. Draw the memory hierarchy in a digital computer. Explain each memory in terms of capacity, size, access time, implementation, and managed by whom.

Memory Hierarchy:

The memory hierarchy is structured as follows:

1. Registers:

   • Capacity: Smallest.
   • Size: Few bytes.
   • Access Time: Fastest.
   • Managed by: CPU.
   • Implementation: Built into the CPU.

2. Cache Memory:

   • Capacity: Small.
   • Size: A few MBs.
   • Access Time: Faster than RAM but slower than registers.
   • Managed by: Hardware.
   • Implementation: High-speed SRAM.

3. Main Memory (RAM):

   • Capacity: Medium.
   • Size: A few GBs.
   • Access Time: Slower than cache.
   • Managed by: Operating System.
   • Implementation: DRAM.

4. Secondary Storage:

   • Capacity: Large.
   • Size: Hundreds of GBs or TBs.
   • Access Time: Slow.
   • Managed by: File System/OS.
   • Implementation: HDDs, SSDs.

5. Tertiary/Backup Storage:

   • Capacity: Very large.
   • Access Time: Slowest.
   • Managed by: User/Backup software.
   • Implementation: Optical disks, tapes.

Diagram:

• Draw a pyramid showing registers at the top and tertiary storage at the base.

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Q12. Draw the circuits of a full adder and discuss its working. Draw its truth table also.

Explanation:

1. Definition:

   • A Full Adder adds three binary inputs: $A$, $B$, and $C_{in}$, and produces two outputs:
     • Sum ($S$).
     • Carry ($C_{out}$).

2. Expressions:

   • Sum: $S = A \oplus B \oplus C_{in}$.
   • Carry: $C_{out} = (A \cdot B) + (C_{in} \cdot (A \oplus B))$.

3. Circuit:

   • Use two XOR gates for the Sum ($S$).
   • Use AND and OR gates for Carry ($C_{out}$).

4. Truth Table:

   A	B	$C_{in}$	Sum ($S$)	Carry ($C_{out}$)
   0	0	0	0	0
   0	0	1	1	0
   0	1	0	1	0
   0	1	1	0	1
   1	0	0	1	0
   1	0	1	0	1
   1	1	0	0	1
   1	1	1	1	1

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Q13. A memory has a capacity of 32K × 8. Find:

(a) The number of words in memory.

• $32K = 32 \times 1024 = 32,768$.
• The number of words = $32,768$.

(b) The number of bits in each word.

• Each word has 8 bits.

(c) The total number of bits in the memory.

• Total bits = Number of words × Bits per word: $$32,768 \times 8 = 262,144 \, \text{bits}.$$

(d) The total number of memory cells in the memory.

• Each bit is stored in one memory cell.
• Total memory cells = Total number of bits: $$262,144 \, \text{cells}.$$

(e) Data input and data output lines.

• Since each word is 8 bits, the memory has:
  • 8 Data Input Lines.
  • 8 Data Output Lines.

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